The present invention relates to nonvolatile semiconductor memory devices, such as a flash EEPROM (electrically erasable and programmable ROM), which store information using hot electrons that are generated in the vicinity of the drain and injected into the floating gate through the gate oxide film.
Referring to FIG. 3, a structure of this type of conventional nonvolatile semiconductor memory device is described below.
In FIG. 3, symbols Tr1 and Tr2 respectively represent a transistor constituting a flash memory cell and a transistor of a peripheral circuit such as a decoder portion. The transistors Tr1 and Tr2 are formed in respective areas on a p-type silicon substrate 1 that are separated by field oxide films 2. The memory cell transistor Tr1 includes a floating gate structure consisting of a floating gate 4, an interlayer insulating film 5 and a control gate 6 that are sequentially formed on a gate oxide film (also called a tunnel oxide film) 3a. The memory cell transistor Tr1 further has a source diffusion layer 7 and a drain diffusion layer 8 that are n.sup.+ diffusion layers formed in the substrate 1 on both sides of the above gate floating structure. The transistor Tr2 of the peripheral circuit consists of a gate electrode 9 formed on a gate oxide film 3b and a source diffusion layer 10 and a drain diffusion layer 11 that are n.sup.+ diffusion layers formed on both sides of the gate electrode 9.
In the flash memory cell having the above structure, hot electrons are generated in the vicinity of the drain diffusion layer 8 by a strong electric field that is formed there by applying a positive high voltage to the control gate 6 and a positive voltage to the drain diffusion layer 8. The hot electrons thus generated are injected into the floating gate 4 through the gate oxide film 3a to provide nonvolatile information storage.
However, the conventional memory device having the above structure is associated with the following problems.
To accommodate the strong requirement for high integration that is imposed on the nonvolatile semiconductor memory devices of the above type, attempts of miniaturizing the constituent semiconductors are now in progress. However, since the peripheral transistor Tr2 of the above memory device has what is called a single drain structure, excessive shortening of the gate length for the miniaturization is likely to increase electric field intensity in the vicinity of the drain diffusion layer 11 and generate hot electrons there. The hot electrons thus generated are trapped in the gate oxide film 3b of the transistor Tr2, and form fixed negative charge, which shifts the threshold voltage of the transistor Tr2 to the positive side, to cause an erroneous operation of a circuit.
To solve the above problem associated with the miniaturization, MOSFETs having what is called a LDD (lightly-doped drain) structure have been proposed in which a low impurity concentration (n.sup.-) layer is provided in the vicinity of the drain diffusion layer 11 to prevent the excessive electric field concentration there. However, if the LDD structure is equally applied to all the transistors constituting the nonvolatile semiconductor memory device, the hot electron generation in the vicinity of the drain diffusion layer 8 of the memory cell transistor Tr1 is also suppressed to cause another kind of problem, i.e., a reduction of the information writing efficiency.